Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a duty cycle correction (DCC) circuit of a semiconductor integrated circuit.
For semiconductor integrated circuits operating based on a clock, such as a semiconductor memory device, it is important to precisely control a duty cycle of the clock. The duty cycle of the clock having a 50% ratio means that a high duration of the clock is substantially the same as a low duration of the clock in a clock cycle.
In case of a semiconductor memory device, data are desired to be accurately input/output in synchronism with rising and falling edges of a clock. When a duty cycle of the clock is not accurately maintained at a 50% ratio, timing between the rising and falling edges of the clock is skewed so that the data is not input/output at accurate timings. Here, an error/offset from 50% ratio reduces a timing margin of a high-performance memory system. Therefore, a duty cycle correction (DCC) circuit is often used in the semiconductor memory device to correct a duty cycle of a clock used in a memory system.
Various methods are used to correct a duty cycle of a clock. For example, a method to correct a duty cycle of a clock by controlling a slew rate of rising and falling edges of the clock is used. Here, the term “slew” is also used to refer to a slew rate which is a rate of voltage change of a signal. The method to correct the duty cycle of the clock by controlling the slew rate of the rising and falling edges of the clock is as follows.
When the slew rate of the rising edge is increased and the slew rate of the falling edge is decreased, a high duration of the clock (that is, high duration period of a clock cycle) becomes longer, i.e., a low duration of the clock shortens. On the contrary, when the slew rate of the rising edge is decreased and the slew rate of the falling edge is increased, a high duration of the clock in a clock cycle becomes shorter, i.e., a low duration of the clock lengthens. As such, the slew rate may be controlled.
In the conventional semiconductor memory device, a digital DCC circuit is often disposed inside a delay locked loop (DLL). In detecting a skew of a duty ratio of a clock, the digital DCC circuit may use two delay chains and two control blocks for controlling two delay chains. Accordingly, the conventional DCC circuit occupies a relatively large area and consumes large current amount.
Further, a conventional DCC circuit using both of a clock and an inverted clock occupies greater area and consumes greater current amount in comparison with a DCC circuit using just one clock. However, in case of the DCC circuit using a clock, it is difficult to control an operation of the DCC circuit.